Conventionally, the Boundary-Scan method has been used for testing a semiconductor device, which is shown in Japanese Patent Publication, Kokai 2001-183420. According to the boundary-scan technique, the specification of the test is determined by, for example, IEEE1149.1. Therefore, the same test pattern signal can be used for a variety of semiconductor device made by different manufactures.
According to a conventional method of test for a semiconductor device, including a memory circuit it is required to carry out tests for the memory circuit and for another logic circuit independently or separately from each other. As a result, it spends a longer period of time to test a semiconductor device, including a memory circuit.